/* * IOport passthough based on the ("port E9") emulation debugcon.c * from https://gitlab.com/qemu-project/qemu/-/blob/master/hw/char/debugcon.c * * This allows a helper software outside QEMU to process read requests and writes to ioport * addresses, preserving the order. * * Copyright (c) 2003-2004 Fabrice Bellard * Copyright (c) 2008 Citrix Systems, Inc. * Copyright (c) Intel Corporation; author: H. Peter Anvin * Copyright (c) 2021-2026 Michael John Wensley * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" #include "chardev/char-fe.h" #include "hw/core/irq.h" #include "hw/isa/isa.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-properties-system.h" #include "qom/object.h" #define TYPE_ISA_IOPORT_DEVICE "isa-ioport" OBJECT_DECLARE_SIMPLE_TYPE(ISAIOPortState, ISA_IOPORT_DEVICE) /* #define DEBUG_IOPORT */ /* we have to do multiregion for the ACPI usecase, typically * first region is part of the GPE0 in order to be able to route irq9 to ACPI * then the main region is the actual dynamic data consumed by the custom SSDP table * and exposed to the guest, such as a virtual battery */ #define IOPORT_REGIONS 2 typedef struct IORegionState { ISAIOPortState *ioportstate; MemoryRegion io; /* as we need to support multiple ranges, store the iobase */ uint32_t iobase; uint32_t iolength; uint32_t iopriority; } IORegionState; struct ISAIOPortState { ISADevice parent_obj; CharFrontend chr; qemu_irq irq[ISA_NUM_IRQS]; IORegionState state[IOPORT_REGIONS]; }; static void ioport_ioport_write(void *opaque, hwaddr addr, uint64_t val, unsigned width) { IORegionState *s = opaque; unsigned char control_octet = 0x8 | ( ( width - 1 ) << 0 ); addr+=s->iobase; #ifdef DEBUG_IOPORT printf(" [ioport: write addr=0x%04" HWADDR_PRIx " val=0x%02" PRIx64 "]\n", addr, val); #endif if (width == 0) return; if (width > 8) return; /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ /* qemu_chr_fe_write_all(&s->ioportstate->chr, &address_size, 1); */ qemu_chr_fe_write_all(&s->ioportstate->chr, &control_octet, 1); static_assert(sizeof(hwaddr) > 1); qemu_chr_fe_write_all(&s->ioportstate->chr, (const unsigned char *)&addr, 2); /* qemu_chr_fe_write_all(&s->ioportstate->chr, &data_size, 1); */ qemu_chr_fe_write_all(&s->ioportstate->chr, (const unsigned char *)&val, width); } /* We are always interested in data from the helper, * if not requested by this module, * it is treated as a request to inject an interrupt */ static int ioport_chr_can_read(void *opaque) { /* IORegionState *s = opaque; */ return 1; } /* especially interested in invoking interrupt 9 acpi, 16550A driver invokes irq by number */ /* isa irq is from 0 to 15 "ISA_NUM_IRQS" */ /* tested with guest /proc/interrupts 9: */ static void ioport_chr_read(void *opaque, const uint8_t *buf, int size) { ISAIOPortState *isa = opaque; #ifdef DEBUG_IOPORT printf(" [ioport: enter ioport_chr_read, with %d]\n", size); #endif if (size) { if (buf[0] < ISA_NUM_IRQS) { qemu_irq_pulse(isa->irq[buf[0]]); } } } static uint64_t ioport_ioport_read(void *opaque, hwaddr addr, unsigned width) { IORegionState *s = opaque; ISAIOPortState *isa = s->ioportstate; uint64_t val = 0xFFFFFFFFFFFFFFFF; /* unsigned char address_size = sizeof(hwaddr); */ /* unsigned char data_size = 0x80 | width; */ unsigned char control_octet = 0x48 | ( ( width - 1 ) << 0 ); addr+=s->iobase; if (width == 0) return 0; if (width > 8) return val; qemu_chr_fe_write_all(&isa->chr, &control_octet, 1); static_assert(sizeof(hwaddr) > 1); qemu_chr_fe_write_all(&isa->chr, (const unsigned char *)&addr, 2); /* qemu_chr_fe_write_all(&isa->chr, &data_size, 1); */ /* avoid a race condition with helper initiated interrupt requests */ while (true) { if (qemu_chr_fe_read_all(&isa->chr, (unsigned char *)&control_octet, 1) != 1) break; if (control_octet == 0xFF) { qemu_chr_fe_read_all(&isa->chr, (unsigned char *)&val, width); break; } if (control_octet < ISA_NUM_IRQS) { qemu_irq_pulse(isa->irq[control_octet]); } } #ifdef DEBUG_IOPORT printf("ioport: read addr=0x%04" HWADDR_PRIx "\n", addr); #endif return val; } /* uint64 implies a maximum width of 8 octets */ static const MemoryRegionOps ioport_ops = { .read = ioport_ioport_read, .write = ioport_ioport_write, .valid.min_access_size = 1, .valid.max_access_size = 8, .endianness = DEVICE_LITTLE_ENDIAN, }; static void ioport_realize_core(ISAIOPortState *isa, Error **errp) { if (!qemu_chr_fe_backend_connected(&isa->chr)) { error_setg(errp, "Can't create ioport device, empty char device"); return; } qemu_chr_fe_set_handlers(&isa->chr, ioport_chr_can_read, ioport_chr_read, NULL, NULL, isa, NULL, true); } static void ioport_isa_realizefn(DeviceState *dev, Error **errp) { ISADevice *d = ISA_DEVICE(dev); ISAIOPortState *isa = ISA_IOPORT_DEVICE(dev); Error *err = NULL; for (int i = 0; i < ISA_NUM_IRQS; i++) { isa->irq[i] = isa_get_irq(d, i); } ioport_realize_core(isa, &err); if (err != NULL) { error_propagate(errp, err); return; } for (int i = 0; i < IOPORT_REGIONS; i++) { IORegionState *s = &isa->state[i]; s->ioportstate = isa; if (s->iolength > 0) { memory_region_init_io(&s->io, OBJECT(dev), &ioport_ops, s, TYPE_ISA_IOPORT_DEVICE, s->iolength); /* upgrade to memory_region_add_subregion_overlap discussed in * https://www.qemu.org/docs/master/devel/memory.html#overlapping-regions-and-priority * to allow seizure of regions claimed by other modules */ memory_region_add_subregion_overlap(isa_address_space_io(d), s->iobase, &s->io, s->iopriority); } } } static const Property ioport_isa_properties[] = { DEFINE_PROP_UINT32("b0", ISAIOPortState, state[0].iobase, 0xe9), DEFINE_PROP_UINT32("l0", ISAIOPortState, state[0].iolength, 1), DEFINE_PROP_UINT32("p0", ISAIOPortState, state[0].iopriority, 0), /* DEFINE_PROP_UINT32("o0", ISAIOPortState, state[0].iooffset, 0), */ DEFINE_PROP_UINT32("b1", ISAIOPortState, state[1].iobase, 0x80), DEFINE_PROP_UINT32("l1", ISAIOPortState, state[1].iolength, 0), DEFINE_PROP_UINT32("p1", ISAIOPortState, state[1].iopriority, 0), /* DEFINE_PROP_UINT32("o1", ISAIOPortState, state[1].iooffset, 1), */ DEFINE_PROP_CHR("chardev", ISAIOPortState, chr), }; static void ioport_isa_class_initfn(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = ioport_isa_realizefn; device_class_set_props(dc, ioport_isa_properties); set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo ioport_isa_info = { .name = TYPE_ISA_IOPORT_DEVICE, .parent = TYPE_ISA_DEVICE, .instance_size = sizeof(ISAIOPortState), .class_init = ioport_isa_class_initfn, }; static void ioport_register_types(void) { type_register_static(&ioport_isa_info); } type_init(ioport_register_types)